1. Field of the Invention
This invention relates to electro-static discharge (ESD) protection techniques and, more particularly, to techniques for providing ESD protection for I/O buffer transistor circuits having open-drain output terminals, even when the I/O buffer transistor circuits are powered down and the bus to which the I/O buffer transistor circuits are connected are active.
2. Prior Art
Conventional CMOS I/O pins contain ESD protection circuitry that clamps the I/O pin to within a diode voltage drop above VDD or below VSS. The protection circuitry makes use of the drain-to-bulk well diodes that are inherent in the structure of the NMOS and PMOS output transistors of the I/O buffer. During normal device operation, these diodes are reverse-biased unless externally applied signal voltages exceed the supply voltage range (VDD-VSS) of the buffer. When a device is powered off, the VDD and VSS pins are effectively at 0 volts, and any positive voltage transition applied to the I/O pins will be clamped by the diode protection circuitry that exits between the I/O pins and VDD pin of the device.
For an open-drain output configuration, only an NMOS pull-down transistor is provided with no complementary PMOS pull-up transistor being provided. In this case, an explicit p+/n- diode or a PMOS transistor (biased off) is usually added to provide EDS protection between the I/O and VDD pins.
Some systems are required to have ESD protection for their output terminals while still permitting the system to be in a powered-down state while the output bus is still active. However, any protection structure that creates a forward-biased diode when the I/O pin voltage is more positive than VDD will not satisfy the power-drown constraint mentioned previously. To satisfy the power-down requirements, prior art implementations utilize an open-drain I/O buffer with no ESD protection structure provided to VDD. This satisfies the power-down constraint but provides no ESD protection between the I/O terminal and the VDD bus.
A need exists for an electro-static discharge ESD protection circuit for a CMOS I/O buffer having an open-drain output.